1. Field of the Invention
The invention pertains to semiconductor devices, and more particularly to vertical double gate MOSFETs, also known as FinFETs.
2. Related Technology
Metal oxide semiconductor field effect transistors (MOSFETs) are the primary component of most semiconductor devices. The conventional MOSFET is comprised of heavily doped source and drain regions that are formed in a semiconductor substrate. The portion of the substrate in which the source and drain regions are formed is lightly doped with a dopant having a conductivity opposite to that of the source and drain regions. As a result, depletion regions form at the junctions of the source and drain regions with the surrounding substrate material, providing electrical isolation of the MOSFET from the substrate and other devices formed in it.
As channel lengths are reduced to less than 100 nm, MOSFETs formed in semiconductor substrates experience performance degrading phenomena such as the short channel effect. The short channel effect degrades the ability of the MOSFET gate to control conductivity in the MOSFET channel region due to interactions of the source and drain regions that occur as a result of the semiconductor substrate materials that surround the source and drain regions.
An alternative to the formation of devices in semiconductor substrates is silicon on insulator (SOI) construction. In SOI construction, the semiconductor material in which the MOSFET is formed overlies a dielectric layer that electrically isolates each device. SOI devices have a number of advantages over devices formed in semiconductor substrates, such as better isolation between devices, reduced leakage current, reduced latch-up between CMOS elements, reduced chip capacitance, and reduction or elimination of short channel coupling between source and drain regions.
One type of MOSFET structure that is formed using SOI construction is conventionally known as a vertical double-gate MOSFET, or a FinFET. As shown in FIG. 1, the FinFET is constructed from a monolithic silicon body that includes a source region 12, a drain region 14 and a fin-shaped channel region 16. The monolithic silicon body is patterned from a silicon layer provided on a dielectric substrate 18. After patterning the silicon body, a gate oxide (not shown) is grown or deposited over the silicon body, and then a conductive gate 20 is patterned so as to surround the channel region 16. The gate 20 is patterned from a conformal layer of a conductive material such as polysilicon. FIG. 2 shows a view of a cross-section of the gate and channel region of the FinFET of FIG. 1. As seen in FIG. 2, the gate 20 and channel region 16 are separated by the gate oxide 22, and the gate 20 surrounds the channel region 16 on both of its sidewalls, thus serving as a double gate that imparts gate voltage to both sides of the channel region 16. The channel width of a FinFET is therefore at least double the height of the channel region 16, enabling a high driving current compared to MOSFETs of comparable size formed in semiconductor substrates. The aspect ratio of the cross section of the channel region 16 is therefore preferably as high as possible so as to form a tall, narrow channel region that provides a maximum effective channel width while keeping the lateral size of the device small.
The substrate from which the conventional SOI device is patterned may be formed in a variety of manners. FIGS. 3a, 3b and 3c show structures formed using implanted oxygen to form a buried oxide (BOX) layer in a silicon substrate. As shown in FIG. 3a, a silicon substrate 24 is provided. The silicon substrate 24 is implanted with oxygen 26 at an energy sufficient to form an oxygenated region 28 at such a depth as to leave a required thickness of silicon above the oxygenated region.
FIG. 3b shows the structure of FIG. 3a after annealing of the silicon substrate 24 to form a buried silicon oxide layer 30 within the substrate. Annealing is typically performed at approximately 1350 degrees C. for approximately four hours. FIG. 3c shows the structure of FIG. 3b after patterning a silicon FinFET body 32 (shown in cross section at the channel region) from the silicon layer that overlies the oxide layer 30.
FIGS. 4a–4d shows structures formed in accordance with a bonding method for forming an SOI substrate. FIG. 4a shows a planarized silicon substrate 34. The substrate 34 is implanted with hydrogen 36 to form a hydrogen rich region 38 within the silicon material. The hydrogen 36 is implanted with an energy such that the amount of silicon remaining above the hydrogen rich region exceeds the thickness of the silicon layer to be formed on the SOI substrate. In some applications a different material such as oxygen may be implanted.
FIG. 4b shows the silicon substrate 34 of FIG. 4a after being cleaned, stripped of oxide in a diluted HF solution, rinsed in deionized water to form an active native oxide on its surface, and then inverted and bonded to a planarized oxide layer 42 formed on a semiconductor layer 44 of second substrate 40. Bonding is generally performed in two stages. In a first stage, the substrates are heated to approximately 600 degrees C. in an inert environment for approximately three hours. As shown in FIG. 4c, the heating of the first stage causes bonding of the silicon 46 of the silicon substrate 34 to the dielectric layer 42 of the substrate 40 due to Van der Waals forces. The heating of the first stage also causes the silicon substrate 34 to fracture along the hydrogen rich region 38, thus leaving a new substrate comprising a silicon layer 46 bonded to an oxide layer 42 and having a residual hydrogen rich region 38 at its upper surface. In a second stage of the bonding process, the bonded structure is heated to approximately 1050–1200 degrees C. for 30 minutes to two hours to strengthen the bond between the dielectric layer 42 and the silicon layer 46. To facilitate bonding, the substrates should be planarized to a homogeneity of 0.5 microns or less. The resulting substrate is then planarized and cleaned, leaving a silicon SOI substrate as shown in FIG. 4d. 
One option for increasing the performance of MOSFETs is to enhance the carrier mobility of the MOSFET semiconductor material so as to reduce resistance and power consumption and to increase drive current, frequency response and operating speed. A method of enhancing carrier mobility that has become a focus of attention is the use of silicon material to which a tensile strain is applied. “Strained” silicon may be formed by growing a layer of silicon on a silicon germanium substrate. The silicon germanium lattice is more widely spaced on average than a pure silicon lattice due to the presence of the larger germanium atoms in the lattice. Because the atoms of the silicon lattice align with the more widely spaced silicon germanium lattice, a tensile strain is created in the silicon layer. The silicon atoms are essentially pulled apart from one another. The amount of tensile strain applied to the silicon lattice increases with the proportion of germanium in the silicon germanium lattice.
The tensile strain applied to the silicon lattice increases carrier mobility. Relaxed silicon has six equal valence bands. The application of tensile strain to the silicon lattice causes four of the valence bands to increase in energy and two of the valence bands to decrease in energy. As a result of quantum effects, electrons effectively weigh 30 percent less when passing through the lower energy bands. Thus the lower energy bands offer less resistance to electron flow. In addition, electrons encounter less vibrational energy from the nucleus of the silicon atom, which causes them to scatter at a rate of 500 to 1000 times less than in relaxed silicon. As a result, carrier mobility is dramatically increased in strained silicon as compared to relaxed silicon, offering a potential increase in mobility of 80% or more for electrons and 20% or more for holes. The increase in mobility has been found to persist for current fields of up to 1.5 megavolts/centimeter. These factors are believed to enable a device speed increase of 35% without further reduction of device size, or a 25% reduction in power consumption without a reduction in performance.
Strained silicon may be used in both silicon substrate and SOI devices. In strained silicon SOI devices, a silicon germanium layer is provided over an insulating substrate, either by the BOX method or by the bonding method, and the silicon germanium is then used as a base upon which strained silicon is grown. A cross-sectional view of a channel region of a strained silicon FinFET structure is shown in FIG. 5. As seen in FIG. 5, the structure comprises a silicon germanium channel region 50 on which is grown an epitaxial layer of strained silicon 52. A gate insulating layer 54 is formed over the strained silicon layer 52, and a double gate structure 56 is formed around the channel portion 50. Thus the structure shown in FIG. 5 forms part of a FinFET that exhibits enhanced carrier mobility as the result of the strained silicon layer provided at the surface of the channel region as well as the source and drain regions.
One detrimental property of SOI construction is that the thermal conductivity of the insulating substrate is significantly less than that of silicon. Heat generated by a MOSFET formed in a silicon substrate is conducted away from the active region through the silicon substrate, which has a relatively good thermal conductivity of 1.5° W/cm-C. In contrast, a silicon oxide substrate has a very poor thermal conductivity of 0.014° W/cm-C. Further, in strained silicon applications, the thermal conductivity of silicon germanium is approximately 0.1° W/cm-C. for a silicon germanium layer having a 20% germanium content, which contributes further to heat dissipation problems. As a result, insufficient dissipation of thermal energy can occur in SOI devices, leading to significant self-heating. Self-heating is known to degrade the I-V characteristics of the MOSFET, such that source-drain current Ids is reduced for a given source-drain voltage Vds.
Therefore the advantages of MOSFETs formed by SOI construction are partly offset by the disadvantages resulting from the poor thermal conductivity of SOI substrates.